coreblocks.arch package

Submodules

coreblocks.arch.csr_address module

class coreblocks.arch.csr_address.CSRAddress

Bases: IntEnum

COREBLOCKS_TEST_CSR = 2047
COREBLOCKS_TEST_EXIT_CSR = 2302
COREBLOCKS_TEST_PRIV_MODE = 2303
CYCLE = 3072
CYCLEH = 3200
DCSR = 1968
DPC = 1969
DSCRATCH0 = 1970
DSCRATCH1 = 1971
FCSR = 3
FFLAGS = 1
FRM = 2
HCONTEXT = 1704
HCOUNTEREN = 1542
HEDELEG = 1538
HEDELEGH = 1554
HENVCFG = 1546
HENVCFGH = 1562
HGATP = 1664
HGEIE = 1543
HGEIP = 3602
HIDELEG = 1539
HIE = 1540
HIP = 1604
HPMCOUNTER10 = 3082
HPMCOUNTER10H = 3210
HPMCOUNTER11 = 3083
HPMCOUNTER11H = 3211
HPMCOUNTER12 = 3084
HPMCOUNTER12H = 3212
HPMCOUNTER13 = 3085
HPMCOUNTER13H = 3213
HPMCOUNTER14 = 3086
HPMCOUNTER14H = 3214
HPMCOUNTER15 = 3087
HPMCOUNTER15H = 3215
HPMCOUNTER16 = 3088
HPMCOUNTER16H = 3216
HPMCOUNTER17 = 3089
HPMCOUNTER17H = 3217
HPMCOUNTER18 = 3090
HPMCOUNTER18H = 3218
HPMCOUNTER19 = 3091
HPMCOUNTER19H = 3219
HPMCOUNTER20 = 3092
HPMCOUNTER20H = 3220
HPMCOUNTER21 = 3093
HPMCOUNTER21H = 3221
HPMCOUNTER22 = 3094
HPMCOUNTER22H = 3222
HPMCOUNTER23 = 3095
HPMCOUNTER23H = 3223
HPMCOUNTER24 = 3096
HPMCOUNTER24H = 3224
HPMCOUNTER25 = 3097
HPMCOUNTER25H = 3225
HPMCOUNTER26 = 3098
HPMCOUNTER26H = 3226
HPMCOUNTER27 = 3099
HPMCOUNTER27H = 3227
HPMCOUNTER28 = 3100
HPMCOUNTER28H = 3228
HPMCOUNTER29 = 3101
HPMCOUNTER29H = 3229
HPMCOUNTER3 = 3075
HPMCOUNTER30 = 3102
HPMCOUNTER30H = 3230
HPMCOUNTER31 = 3103
HPMCOUNTER31H = 3231
HPMCOUNTER3H = 3203
HPMCOUNTER4 = 3076
HPMCOUNTER4H = 3204
HPMCOUNTER5 = 3077
HPMCOUNTER5H = 3205
HPMCOUNTER6 = 3078
HPMCOUNTER6H = 3206
HPMCOUNTER7 = 3079
HPMCOUNTER7H = 3207
HPMCOUNTER8 = 3080
HPMCOUNTER8H = 3208
HPMCOUNTER9 = 3081
HPMCOUNTER9H = 3209
HSTATEEN0 = 1548
HSTATEEN0H = 1564
HSTATEEN1 = 1549
HSTATEEN1H = 1565
HSTATEEN2 = 1550
HSTATEEN2H = 1566
HSTATEEN3 = 1551
HSTATEEN3H = 1567
HSTATUS = 1536
HTIMEDELTA = 1541
HTIMEDELTAH = 1557
HTINST = 1610
HTVAL = 1603
HVIP = 1605
INSTRET = 3074
INSTRETH = 3202
MARCHID = 3858
MCAUSE = 834
MCONFIGPTR = 3861
MCONTEXT = 1960
MCOUNTEREN = 774
MCOUNTINHIBIT = 800
MCYCLE = 2816
MCYCLEH = 2944
MEDELEG = 770
MEDELEGH = 786
MENVCFG = 778
MENVCFGH = 794
MEPC = 833
MHARTID = 3860
MHPMCOUNTER10 = 2826
MHPMCOUNTER10H = 2954
MHPMCOUNTER11 = 2827
MHPMCOUNTER11H = 2955
MHPMCOUNTER12 = 2828
MHPMCOUNTER12H = 2956
MHPMCOUNTER13 = 2829
MHPMCOUNTER13H = 2957
MHPMCOUNTER14 = 2830
MHPMCOUNTER14H = 2958
MHPMCOUNTER15 = 2831
MHPMCOUNTER15H = 2959
MHPMCOUNTER16 = 2832
MHPMCOUNTER16H = 2960
MHPMCOUNTER17 = 2833
MHPMCOUNTER17H = 2961
MHPMCOUNTER18 = 2834
MHPMCOUNTER18H = 2962
MHPMCOUNTER19 = 2835
MHPMCOUNTER19H = 2963
MHPMCOUNTER20 = 2836
MHPMCOUNTER20H = 2964
MHPMCOUNTER21 = 2837
MHPMCOUNTER21H = 2965
MHPMCOUNTER22 = 2838
MHPMCOUNTER22H = 2966
MHPMCOUNTER23 = 2839
MHPMCOUNTER23H = 2967
MHPMCOUNTER24 = 2840
MHPMCOUNTER24H = 2968
MHPMCOUNTER25 = 2841
MHPMCOUNTER25H = 2969
MHPMCOUNTER26 = 2842
MHPMCOUNTER26H = 2970
MHPMCOUNTER27 = 2843
MHPMCOUNTER27H = 2971
MHPMCOUNTER28 = 2844
MHPMCOUNTER28H = 2972
MHPMCOUNTER29 = 2845
MHPMCOUNTER29H = 2973
MHPMCOUNTER3 = 2819
MHPMCOUNTER30 = 2846
MHPMCOUNTER30H = 2974
MHPMCOUNTER31 = 2847
MHPMCOUNTER31H = 2975
MHPMCOUNTER3H = 2947
MHPMCOUNTER4 = 2820
MHPMCOUNTER4H = 2948
MHPMCOUNTER5 = 2821
MHPMCOUNTER5H = 2949
MHPMCOUNTER6 = 2822
MHPMCOUNTER6H = 2950
MHPMCOUNTER7 = 2823
MHPMCOUNTER7H = 2951
MHPMCOUNTER8 = 2824
MHPMCOUNTER8H = 2952
MHPMCOUNTER9 = 2825
MHPMCOUNTER9H = 2953
MHPMEVENT10 = 810
MHPMEVENT10H = 1834
MHPMEVENT11 = 811
MHPMEVENT11H = 1835
MHPMEVENT12 = 812
MHPMEVENT12H = 1836
MHPMEVENT13 = 813
MHPMEVENT13H = 1837
MHPMEVENT14 = 814
MHPMEVENT14H = 1838
MHPMEVENT15 = 815
MHPMEVENT15H = 1839
MHPMEVENT16 = 816
MHPMEVENT16H = 1840
MHPMEVENT17 = 817
MHPMEVENT17H = 1841
MHPMEVENT18 = 818
MHPMEVENT18H = 1842
MHPMEVENT19 = 819
MHPMEVENT19H = 1843
MHPMEVENT20 = 820
MHPMEVENT20H = 1844
MHPMEVENT21 = 821
MHPMEVENT21H = 1845
MHPMEVENT22 = 822
MHPMEVENT22H = 1846
MHPMEVENT23 = 823
MHPMEVENT23H = 1847
MHPMEVENT24 = 824
MHPMEVENT24H = 1848
MHPMEVENT25 = 825
MHPMEVENT25H = 1849
MHPMEVENT26 = 826
MHPMEVENT26H = 1850
MHPMEVENT27 = 827
MHPMEVENT27H = 1851
MHPMEVENT28 = 828
MHPMEVENT28H = 1852
MHPMEVENT29 = 829
MHPMEVENT29H = 1853
MHPMEVENT3 = 803
MHPMEVENT30 = 830
MHPMEVENT30H = 1854
MHPMEVENT31 = 831
MHPMEVENT31H = 1855
MHPMEVENT3H = 1827
MHPMEVENT4 = 804
MHPMEVENT4H = 1828
MHPMEVENT5 = 805
MHPMEVENT5H = 1829
MHPMEVENT6 = 806
MHPMEVENT6H = 1830
MHPMEVENT7 = 807
MHPMEVENT7H = 1831
MHPMEVENT8 = 808
MHPMEVENT8H = 1832
MHPMEVENT9 = 809
MHPMEVENT9H = 1833
MIDELEG = 771
MIE = 772
MIMPID = 3859
MINSTRET = 2818
MINSTRETH = 2946
MIP = 836
MISA = 769
MNCAUSE = 1858
MNEPC = 1857
MNSCRATCH = 1856
MNSTATUS = 1860
MSCRATCH = 832
MSECCFG = 1863
MSECCFGH = 1879
MSTATEEN0 = 780
MSTATEEN0H = 796
MSTATEEN1 = 781
MSTATEEN1H = 797
MSTATEEN2 = 782
MSTATEEN2H = 798
MSTATEEN3 = 783
MSTATEEN3H = 799
MSTATUS = 768
MSTATUSH = 784
MTINST = 842
MTVAL = 835
MTVAL2 = 843
MTVEC = 773
MVENDORID = 3857
PMPADDR0 = 944
PMPADDR1 = 945
PMPADDR10 = 954
PMPADDR11 = 955
PMPADDR12 = 956
PMPADDR13 = 957
PMPADDR14 = 958
PMPADDR15 = 959
PMPADDR16 = 960
PMPADDR17 = 961
PMPADDR18 = 962
PMPADDR19 = 963
PMPADDR2 = 946
PMPADDR20 = 964
PMPADDR21 = 965
PMPADDR22 = 966
PMPADDR23 = 967
PMPADDR24 = 968
PMPADDR25 = 969
PMPADDR26 = 970
PMPADDR27 = 971
PMPADDR28 = 972
PMPADDR29 = 973
PMPADDR3 = 947
PMPADDR30 = 974
PMPADDR31 = 975
PMPADDR32 = 976
PMPADDR33 = 977
PMPADDR34 = 978
PMPADDR35 = 979
PMPADDR36 = 980
PMPADDR37 = 981
PMPADDR38 = 982
PMPADDR39 = 983
PMPADDR4 = 948
PMPADDR40 = 984
PMPADDR41 = 985
PMPADDR42 = 986
PMPADDR43 = 987
PMPADDR44 = 988
PMPADDR45 = 989
PMPADDR46 = 990
PMPADDR47 = 991
PMPADDR48 = 992
PMPADDR49 = 993
PMPADDR5 = 949
PMPADDR50 = 994
PMPADDR51 = 995
PMPADDR52 = 996
PMPADDR53 = 997
PMPADDR54 = 998
PMPADDR55 = 999
PMPADDR56 = 1000
PMPADDR57 = 1001
PMPADDR58 = 1002
PMPADDR59 = 1003
PMPADDR6 = 950
PMPADDR60 = 1004
PMPADDR61 = 1005
PMPADDR62 = 1006
PMPADDR63 = 1007
PMPADDR7 = 951
PMPADDR8 = 952
PMPADDR9 = 953
PMPCFG0 = 928
PMPCFG1 = 929
PMPCFG10 = 938
PMPCFG11 = 939
PMPCFG12 = 940
PMPCFG13 = 941
PMPCFG14 = 942
PMPCFG15 = 943
PMPCFG2 = 930
PMPCFG3 = 931
PMPCFG4 = 932
PMPCFG5 = 933
PMPCFG6 = 934
PMPCFG7 = 935
PMPCFG8 = 936
PMPCFG9 = 937
SATP = 384
SCAUSE = 322
SCONTEXT = 1448
SCOUNTEREN = 262
SCOUNTINHIBIT = 288
SCOUNTOVF = 3488
SENVCFG = 266
SEPC = 321
SIE = 260
SIP = 324
SSCRATCH = 320
SSP = 17
SSTATEEN0 = 268
SSTATEEN1 = 269
SSTATEEN2 = 270
SSTATEEN3 = 271
SSTATUS = 256
STIMECMP = 333
STIMECMPH = 349
STVAL = 323
STVEC = 261
TDATA1 = 1953
TDATA2 = 1954
TDATA3 = 1955
TIME = 3073
TIMEH = 3201
TSELECT = 1952
VSATP = 640
VSCAUSE = 578
VSEPC = 577
VSIE = 516
VSIP = 580
VSSCRATCH = 576
VSSTATUS = 512
VSTVAL = 579
VSTVEC = 517
__new__(value)
class coreblocks.arch.csr_address.CounterEnableFieldOffsets

Bases: IntEnum

CY = 0
HPM10 = 10
HPM11 = 11
HPM12 = 12
HPM13 = 13
HPM14 = 14
HPM15 = 15
HPM16 = 16
HPM17 = 17
HPM18 = 18
HPM19 = 19
HPM20 = 20
HPM21 = 21
HPM22 = 22
HPM23 = 23
HPM24 = 24
HPM25 = 25
HPM26 = 26
HPM27 = 27
HPM28 = 28
HPM29 = 29
HPM3 = 3
HPM30 = 30
HPM31 = 31
HPM4 = 4
HPM5 = 5
HPM6 = 6
HPM7 = 7
HPM8 = 8
HPM9 = 9
IR = 2
TM = 1
__new__(value)
class coreblocks.arch.csr_address.MenvcfgFieldOffsets

Bases: IntEnum

ADUE = 61
CBCFE = 6
CBIE = 4
CBZE = 7
CDE = 60
DTE = 59
FIOM = 0
LPE = 2
PBMTE = 62
PMM = 32
SSE = 3
STCE = 63
__new__(value)
field_length() → int
class coreblocks.arch.csr_address.MstatusFieldOffsets

Bases: IntEnum

FS = 13
GVA = 38
MBE = 37
MDT = 41
MIE = 3
MPELP = 40
MPIE = 7
MPP = 11
MPRV = 17
MPV = 39
MXR = 19
SBE = 36
SD = -1
SDT = 24
SIE = 1
SPELP = 23
SPIE = 5
SPP = 8
SUM = 18
SXL = 34
TSR = 22
TVM = 20
TW = 21
UBE = 6
UXL = 32
VS = 9
XS = 15
__new__(value)
field_length() → int

coreblocks.arch.isa module

class coreblocks.arch.isa.Extension

Bases: IntFlag

Enum of available RISC-V extensions.

Extensions are ordered by ISA naming convention: IMAFDQLCBKJTPVH, Z[category letter order]*, S[vshm]*, X*

A = 8

Atomic operations

B = 512

Bit manipulation operations

C = 256

16-bit compressed instructions

D = 32

Double precision floating-point operations (64-bit)

E = 1

Reduced integer operations

F = 16

Single precision floating-point operations (32-bit)

G = 393278

General extension containing all basic operations

I = 2

Full integer operations

J = 1024

Dynamic languages

L = 128

Decimal floating-point operation

M = 4

Integer multiplication and division

N = 16384

User-level interruptions

P = 4096

Packed-SIMD extensions

Q = 64

Quad precision floating-point operations (128-bit)

T = 2048

Transactional memory

V = 8192

Vector operations

XINTMACHINEMODE = 2199023255552

Coreblocks internal categorizing extension: Machine-Mode Privilieged Instructions

XINTSUPERVISOR = 4398046511104

Coreblocks internal categorizing extension: Supervisor Instructions

ZAAMO = 8388608

Atomic memory operations

ZALRSC = 16777216

Load-Reserved/Store-Conditional Instructions

ZAM = 33554432

Misaligned atomic operations

ZBA = 2147483648

Extended shift operations

ZBB = 68719476736

Basic bit manipulation operations

ZBC = 137438953472

Carry-less multiplication operations

ZBKX = 274877906944

Crossbar permutation operations

ZBS = 549755813888

Single bit operations

ZCA = 4294967296

Compressed integer instructions (16-bit, formerly part of C)

ZCB = 34359738368

Compressed simple code-size reduction instructions

ZCD = 17179869184

Compressed floating-point double instructions (formerly part of C if D enabled)

ZCF = 8589934592

Compressed single-precision floating-point instructions (formerly part of C if F enabled)

ZDINX = 536870912

Support for double precision floating-point operations in integer registers

ZFH = 67108864

Half precision floating-point operations (16-bit)

ZFHMIN = 134217728

Minimal support for Half precision floating-point operations (16-bit)

ZFINX = 268435456

Support for single precision floating-point operations in integer registers

ZHINX = 1073741824

Support for half precision floating-point operations in integer registers

ZICNTR = 32768

Enables base counters and timers

ZICOND = 65536

Integer conditional operations

ZICSR = 131072

Control and Status Register access

ZIFENCEI = 262144

Instruction-Fetch fence operations

ZIHINTNTL = 524288

Enables non-temporal locality hints

ZIHINTPAUSE = 1048576

Enables sending pause hint for energy saving

ZIHPM = 2097152

Enables hardware performance counters

ZMMUL = 4194304

Integer multiplication operations

ZTSO = 1099511627776

Total store ordering

__new__(value)
class coreblocks.arch.isa.ISA

Bases: object

ISA is a class that gathers all ISA-specific configurations.

For each of the numeric configuration value val, a corresponding val_log field is provided if relevant.

Attributes:
xlenint

Native integer register width.

reg_cnt:

Number of integer registers.

ilen:

Maximum instruction length.

csr_alen:

CSR address width.

extensions:

All supported extensions in the form of a bitwise or of Extension.

__init__(extensions: Extension, xlen: int)
gen_str(*, skip_internal: bool = False, skip_implied: bool = False) → str

coreblocks.arch.isa_consts module

class coreblocks.arch.isa_consts.ExceptionCause

Bases: IntEnum

BREAKPOINT = 3
ENVIRONMENT_CALL_FROM_M = 11
ENVIRONMENT_CALL_FROM_S = 9
ENVIRONMENT_CALL_FROM_U = 8
ILLEGAL_INSTRUCTION = 2
INSTRUCTION_ACCESS_FAULT = 1
INSTRUCTION_ADDRESS_MISALIGNED = 0
INSTRUCTION_PAGE_FAULT = 12
LOAD_ACCESS_FAULT = 5
LOAD_ADDRESS_MISALIGNED = 4
LOAD_PAGE_FAULT = 13
STORE_ACCESS_FAULT = 7
STORE_ADDRESS_MISALIGNED = 6
STORE_PAGE_FAULT = 15
__new__(value)
classmethod smode_delegable_mask(xlen: int) → int
class coreblocks.arch.isa_consts.FenceFm

Bases: Enum

NONE = 0
TSO = 8
__new__(value)
class coreblocks.arch.isa_consts.FenceTarget

Bases: Flag

DEV_I = 8
DEV_O = 4
MEM_R = 2
MEM_W = 1
__new__(value)
class coreblocks.arch.isa_consts.Funct12

Bases: IntEnum

CLZ = 1536
CPOP = 1538
CTZ = 1537
EBREAK = 1
ECALL = 0
MRET = 770
ORCB = 647
REV8_32 = 1688
REV8_64 = 1720
SEXTB = 1540
SEXTH = 1541
SRET = 258
WFI = 261
ZEXTH = 128
__new__(value)
class coreblocks.arch.isa_consts.Funct3

Bases: IntEnum

ADD = 0
AND = 7
ANDN = 7
B = 0
BCLR = 1
BEQ = 0
BEXT = 5
BGE = 5
BGEU = 7
BINV = 1
BLT = 4
BLTU = 6
BNE = 1
BSET = 1
BU = 4
CLMUL = 1
CLMULH = 3
CLMULR = 2
CLZ = 1
CPOP = 1
CSRRC = 3
CSRRCI = 7
CSRRS = 2
CSRRSI = 6
CSRRW = 1
CSRRWI = 5
CTZ = 1
CZEROEQZ = 5
CZERONEZ = 7
D = 3
DIV = 4
DIVU = 5
DIVUW = 5
DIVW = 4
FENCE = 0
FENCEI = 1
H = 1
HU = 5
JALR = 0
MAX = 6
MAXU = 7
MIN = 4
MINU = 5
MUL = 0
MULH = 1
MULHSU = 2
MULHU = 3
MULW = 0
OR = 6
ORCB = 5
ORN = 6
PRIV = 0
REM = 6
REMU = 7
REMUW = 7
REMW = 6
REV8 = 5
ROL = 1
ROR = 5
SEXTB = 1
SEXTH = 1
SH1ADD = 2
SH2ADD = 4
SH3ADD = 6
SLL = 1
SLT = 2
SLTU = 3
SR = 5
SUB = 0
W = 2
XNOR = 4
XOR = 4
XPERM4 = 2
XPERM8 = 4
ZEXTH = 4
__new__(value)
class coreblocks.arch.isa_consts.Funct7

Bases: IntEnum

ADD = 0
AMOADD = 0
AMOAND = 48
AMOMAX = 80
AMOMAXU = 112
AMOMIN = 64
AMOMINU = 96
AMOOR = 32
AMOSWAP = 4
AMOXOR = 16
AND = 0
ANDN = 32
BCLR = 36
BEXT = 36
BINV = 52
BSET = 20
CLMUL = 5
CLZ = 48
CPOP = 48
CTZ = 48
CZERO = 7
LR = 8
MAX = 5
MIN = 5
MULDIV = 1
OR = 0
ORCB = 20
ORN = 32
REV8 = 52
ROL = 48
ROR = 48
SA = 32
SC = 12
SEXTB = 48
SEXTH = 48
SFENCEVMA = 9
SH1ADD = 16
SH2ADD = 16
SH3ADD = 16
SL = 0
SLT = 0
SUB = 32
XNOR = 32
XOR = 0
XPERM = 20
ZEXTH = 4
__new__(value)
class coreblocks.arch.isa_consts.HPMEvent

Bases: IntEnum

Implementation-defined hardware performance monitoring event numbers, selectable via the mhpmeventN CSRs.

BRANCH_MISPREDICTION = 1
NO_EVENT = 0
__new__(value)
class coreblocks.arch.isa_consts.InstrType

Bases: Enum

B = 3
I = 1
J = 5
R = 0
S = 2
U = 4
__new__(value)
class coreblocks.arch.isa_consts.InterruptCauseNumber

Bases: IntEnum

MEI = 11
MSI = 3
MTI = 7
SEI = 9
SSI = 1
STI = 5
__new__(value)
class coreblocks.arch.isa_consts.Opcode

Bases: Enum

AMO = 11
AUIPC = 5
BRANCH = 24
JAL = 27
JALR = 25
LOAD = 0
LOAD_FP = 1
LUI = 13
MISC_MEM = 3
OP = 12
OP32 = 14
OP_IMM = 4
OP_IMM_32 = 6
RESERVED = 31
STORE = 8
STORE_FP = 9
SYSTEM = 28
__new__(value)
class coreblocks.arch.isa_consts.PMPAFlagEncoding

Bases: Enum

NA4 = 2
NAPOT = 3
OFF = 0
TOR = 1
__new__(value)
class coreblocks.arch.isa_consts.PMPCfgLayout

Bases: StructLayout

__init__()
class coreblocks.arch.isa_consts.PrivilegeLevel

Bases: IntEnum

MACHINE = 3
SUPERVISOR = 1
USER = 0
__new__(value)
class coreblocks.arch.isa_consts.Registers

Bases: IntEnum

A0 = 10
A1 = 11
A2 = 12
A3 = 13
A4 = 14
A5 = 15
A6 = 16
A7 = 17
FP = 8
GP = 3
RA = 1
S0 = 8
S1 = 9
S10 = 26
S11 = 27
S2 = 18
S3 = 19
S4 = 20
S5 = 21
S6 = 22
S7 = 23
S8 = 24
S9 = 25
SP = 2
T0 = 5
T1 = 6
T2 = 7
T3 = 28
T4 = 29
T5 = 30
T6 = 31
TP = 4
X0 = 0
X1 = 1
X10 = 10
X11 = 11
X12 = 12
X13 = 13
X14 = 14
X15 = 15
X16 = 16
X17 = 17
X18 = 18
X19 = 19
X2 = 2
X20 = 20
X21 = 21
X22 = 22
X23 = 23
X24 = 24
X25 = 25
X26 = 26
X27 = 27
X28 = 28
X29 = 29
X3 = 3
X30 = 30
X31 = 31
X4 = 4
X5 = 5
X6 = 6
X7 = 7
X8 = 8
X9 = 9
ZERO = 0
__new__(value)
class coreblocks.arch.isa_consts.XlenEncoding

Bases: Enum

W128 = 3
W32 = 1
W64 = 2
__new__(value)
static from_xlen(xlen: int)

coreblocks.arch.optypes module

class coreblocks.arch.optypes.CfiType

Bases: Enum

Types of control flow instructions.

BRANCH = 1
INVALID = 0
JAL = 3
JALR = 2
__new__(value)
class coreblocks.arch.optypes.OpType

Bases: IntEnum

Enum of operation types. Do not confuse with Opcode.

ADDRESS_GENERATION = 27
ARITHMETIC = 19
ATOMIC_LR_SC = 7
ATOMIC_MEMORY_OP = 6
AUIPC = 23
BIT_MANIPULATION = 28
BIT_ROTATION = 29
BRANCH = 3
CLMUL = 36
COMPARE = 20
CROSSBAR_PERMUTATION = 35
CSR_IMM = 17
CSR_REG = 16
CZERO = 37
DIV_REM = 25
EBREAK = 9
ECALL = 8
EXCEPTION = 18

Internal Coreblocks OpType, specifying that instruction caused Exception before FU execution

FENCE = 13
FENCEI = 14
JAL = 1
JALR = 2
LOAD = 4
LOGIC = 21
MRET = 10
MUL = 24
SFENCEVMA = 15
SHIFT = 22
SINGLE_BIT_MANIPULATION = 26
SRET = 11
STORE = 5
UNARY_BIT_MANIPULATION_1 = 30
UNARY_BIT_MANIPULATION_2 = 31
UNARY_BIT_MANIPULATION_3 = 32
UNARY_BIT_MANIPULATION_4 = 33
UNARY_BIT_MANIPULATION_5 = 34
UNKNOWN = 0
WFI = 12
__new__(value)
class coreblocks.arch.optypes.RasAction

Bases: Flag

Effect a control flow instruction has on the return address stack.

NONE = 0
POP = 1
POP_AND_PUSH = 3
PUSH = 2
__new__(value)
static has_pop(val: Value | int | Enum | ValueCastable) → Value
static has_push(val: Value | int | Enum | ValueCastable) → Value

Module contents