coreblocks package

Subpackages

Submodules

coreblocks.core module

class coreblocks.core.Core

Bases: Component

__init__(*, gen_params: GenParams)

interrupts: Signal

wb_data: WishboneInterface

wb_instr: WishboneInterface

coreblocks.gen_verilog module

coreblocks.gen_verilog.gen_verilog(core_config: CoreConfiguration, output_path: str, *, wrap_socks: bool = False, enable_vivado_hacks: bool = False, sim_logs: tuple[int, str] | None = None)

coreblocks.gen_verilog.main()

Module contents