coreblocks.peripherals package

Submodules

coreblocks.peripherals.axi_lite module

class coreblocks.peripherals.axi_lite.AXILiteInterface

Bases: AbstractInterface[AbstractSignature], Protocol

read_address: AXILiteReadAddressInterface

read_data: AXILiteReadDataInterface

write_address: AXILiteWriteAddressInterface

write_data: AXILiteWriteDataInterface

write_response: AXILiteWriteResponseInterface

class coreblocks.peripherals.axi_lite.AXILiteMaster

Bases: Component

AXI-Lite master interface.

Parameters

axil_params: AXILiteParameters: Parameters for bus generation.

Attributes

ra_request: Method: Transactional method for initiating request on read address channel. Ready when no request or only one is being executed. Takes ‘ra_request_layout’ as argument.
rd_response: Method: Transactional method for reading response from read data channel. Ready when there is request response availabe. Returns data and response state as ‘rd_response_layout’.
wa_request: Method: Transactional method for initiating request on write address channel. Ready when no request or only one is being executed. Takes ‘wa_request_layout’ as argument.
wd_request: Method: Transactional method for initiating request on write data channel. Ready when no request or only one is being executed. Takes ‘wd_request_layout’ as argument.
wr_response: Method: Transactional method for reading response from write response channel. Ready when there is request response availabe. Returns response state as ‘wr_response_layout’.

__init__(axil_params: AXILiteParameters)

axil_master: AXILiteInterface

result_handler(m: TModule, forwarder: Forwarder, *, channel: coreblocks.peripherals.axi_lite.AXILiteWriteResponseInterface | coreblocks.peripherals.axi_lite.AXILiteReadDataInterface)

start_request_transaction(m, arg, *, channel, is_address_channel)

state_machine_request(m: TModule, method: Method, *, channel: coreblocks.peripherals.axi_lite.AXILiteWriteAddressInterface | coreblocks.peripherals.axi_lite.AXILiteWriteDataInterface | coreblocks.peripherals.axi_lite.AXILiteReadAddressInterface, request_signal: Signal)

class coreblocks.peripherals.axi_lite.AXILiteParameters

Bases: object

Parameters of the AXI-Lite bus.

Parameters

data_width: int: Width of “data” signals for “write data” and “read data” channels. Must be either 32 or 64 bits. Defaults to 64
addr_width: int: Width of “addr” signals for “write address” and “read address” channels. Defaults to 64 bits.

__init__(*, data_width: int = 64, addr_width: int = 64)

class coreblocks.peripherals.axi_lite.AXILiteSignature

Bases: Signature

AXI-Lite bus signature

Parameters

axil_params: AXILiteParameters: Patameters used to generate AXI-Lite signature

__init__(axil_params: AXILiteParameters)

coreblocks.peripherals.bus_adapter module

class coreblocks.peripherals.bus_adapter.AXILiteMasterAdapter

Bases: Elaboratable, BusMasterInterface

An adapter for AXI Lite master.

The adapter module is for use in places where BusMasterInterface is expected.

Parameters

bus: AXILiteMaster: Specific AXI Lite master module which is to be adapted.

Attributes

params: BusParametersInterface: Parameters of the bus.
method_layouts: CommonBusMasterMethodLayout: Layouts of common bus master methods.
request_read: Method: Transactional method for initiating a read request. It is ready if the ra_request method of the underlying AXI Lite master is ready. Input layout is request_read_layout.
request_write: Method: Transactional method for initiating a write request. It is ready if the ‘wa_request’ and ‘wd_request’ methods of the underlying AXI Lite master are ready. Input layout is request_write_layout.
get_read_response: Method: Transactional method for reading a response of a read action. It is ready if the rd_response method of the underlying AXI Lite master is ready. Output layout is read_response_layout.
get_write_response: Method: Transactional method for reading a response of a write action. It is ready if the wr_response method of the underlying AXI Lite master is ready. Output layout is write_response_layout.

__init__(bus: AXILiteMaster)

class coreblocks.peripherals.bus_adapter.BusMasterInterface

Bases: HasElaborate, Protocol

An interface of a common bus.

The bus interface is the preferred way to gain access to a specific bus. It simplifies interchangeability of buses on the core configuration level.

Parameters

paramsBusParametersInterface: Parameters of the bus.
request_readMethod: A method that is used to send a read request to a bus.
request_writeMethod: A method that is used to send a write request to a bus.
get_read_responseMethod: A method that is used to receive a response from a bus for a previously sent read request.
get_write_responseMethod: A method that is used to receive a response from a bus for a previously sent write request.

get_read_response: Method

get_write_response: Method

params: BusParametersInterface

request_read: Method

request_write: Method

class coreblocks.peripherals.bus_adapter.WishboneMasterAdapter

Bases: Elaboratable, BusMasterInterface

An adapter for Wishbone master.

The adapter module is for use in places where BusMasterInterface is expected.

Parameters

bus: WishboneMaster: Specific Wishbone master module which is to be adapted.

Attributes

params: BusParametersInterface: Parameters of the bus.
method_layouts: CommonBusMasterMethodLayout: Layouts of common bus master methods.
request_read: Method: Transactional method for initiating a read request. It is ready if the request method of the underlying Wishbone master is ready. Input layout is request_read_layout.
request_write: Method: Transactional method for initiating a write request. It is ready if the request method of the underlying Wishbone master is ready. Input layout is request_write_layout.
get_read_response: Method: Transactional method for reading a response of a read action. It is ready if the result method of the underlying Wishbone master is ready. Output layout is read_response_layout.
get_write_response: Method: Transactional method for reading a response of a write action. It is ready if the result method of the underlying Wishbone master is ready. Output layout is write_response_layout.

__init__(bus: WishboneMaster)

coreblocks.peripherals.wishbone module

class coreblocks.peripherals.wishbone.PipelinedWishboneMaster

Bases: Component

Pipelined Wishbone bus master interface.

Parameters

wb_params: WishboneParameters: Parameters for bus generation.
max_req: int: Size of the response buffer, limits the number of pending requests. Defaults to 8.

Attributes

wb: WishboneInterface: Wishbone bus output.
request: Method: Transactional method to start a new Wishbone request. Ready if new request can be immediately sent. Takes request_layout as argument.
result: Method: Transactional method to read results from completed requests sequentially. Ready if buffered results are available. Returns state of request (error or success) and data (in case of read request) as result_layout.
requests_finished: Signal, out: True, if there are no requests waiting for response

__init__(wb_params: WishboneParameters, *, max_req: int = 8)

generate_method_layouts(wb_params: WishboneParameters)

wb: WishboneInterface

class coreblocks.peripherals.wishbone.WishboneArbiter

Bases: Component

Wishbone Arbiter.

Connects multiple masters to one slave. Bus is requested by asserting CYC signal and is granted to masters in a round robin manner.

Parameters

wb_params: WishboneParameters: Parameters for bus generation.
num_slaves: int: Number of master devices.

Attributes

slave_wb: WishboneInterface: Slave inteface.
masters: list of WishboneInterface: List of master interfaces.

__init__(wb_params: WishboneParameters, num_masters: int)

masters: list[coreblocks.peripherals.wishbone.WishboneInterface]

slave_wb: WishboneInterface

class coreblocks.peripherals.wishbone.WishboneInterface

Bases: AbstractInterface[AbstractSignature], Protocol

ack: Signal

adr: Signal

cyc: Signal

dat_r: Signal

dat_w: Signal

err: Signal

lock: Signal

rst: Signal

rty: Signal

sel: Signal

stall: Signal

stb: Signal

we: Signal

class coreblocks.peripherals.wishbone.WishboneMaster

Bases: Component

Wishbone bus master interface.

Parameters

wb_params: WishboneParameters: Parameters for bus generation.
name: str, optional: Name of this bus. Used for logging.

Attributes

wb_master: WishboneInterface: Wishbone bus output.
request: Method: Transactional method to start a new Wishbone request. Ready when no request is being executed and previous result is read. Takes request_layout as argument.
result: Method: Transactional method to read previous request result. Becomes ready after Wishbone request is completed. Returns state of request (error or success) and data (in case of read request) as result_layout.

__init__(wb_params: WishboneParameters, name: str = '')

wb_master: WishboneInterface

class coreblocks.peripherals.wishbone.WishboneMasterMethodLayout

Bases: object

Wishbone master layouts for methods

Parameters

wb_params: WishboneParameters: Patameters used to generate Wishbone master layouts

Attributes

request_layout: Layout: Layout for request method of WishboneMaster.
result_layout: Layout: Layout for result method of WishboneMaster.

__init__(wb_params: WishboneParameters)

class coreblocks.peripherals.wishbone.WishboneMemorySlave

Bases: Component

Wishbone slave with memory Wishbone slave interface with addressable memory underneath.

Parameters

wb_params: WishboneParameters: Parameters for bus generation.
**kwargs: dict: Keyword arguments for the underlying Amaranth’s Memory. If width and depth are not specified, then they’re inferred from wb_params: data_width becomes width and 2 ** addr_width becomes depth.

Attributes

bus: WishboneInterface: Wishbone bus interface.

__init__(wb_params: WishboneParameters, **kwargs)

bus: WishboneInterface

class coreblocks.peripherals.wishbone.WishboneMuxer

Bases: Component

Wishbone Muxer.

Connects one master to multiple slaves.

Parameters

wb_params: WishboneParameters: Parameters for bus generation.
num_slaves: int: Number of slave devices to multiplex.
ssel_tga: Signal: Signal that selects the slave to connect. Signal width is the number of slaves and each bit coresponds to a slave. This signal is a Wishbone TGA (address tag), so it needs to be valid every time Wishbone STB is asserted. Note that if Pipelined Wishbone implementation is used, then before staring any new request with different ssel_tga value, all pending request have to be finished (and stall cleared) and there have to be one cycle delay from previouse request (to deassert the STB signal). Holding new requests should be implemented in block that controlls ssel_tga signal, before the Wishbone Master.

Attributes

master_wb: WishboneInterface: Master inteface.
slaves: list of WishboneInterface: List of connected slaves’ Wishbone interfaces.

__init__(wb_params: WishboneParameters, num_slaves: int, ssel_tga: Signal)

master_wb: WishboneInterface

slaves: list[coreblocks.peripherals.wishbone.WishboneInterface]

class coreblocks.peripherals.wishbone.WishboneParameters

Bases: object

Parameters of the Wishbone bus.

Parameters

data_width: int: Width of dat_r and dat_w Wishbone signals. Defaults to 64 bits
addr_width: int: Width of adr Wishbone singal. Defaults to 64 bits
granularity: int: The smallest unit of data transfer that a port is capable of transferring. Defaults to 8 bits

__init__(*, data_width: int = 64, addr_width: int = 64, granularity: int = 8)

class coreblocks.peripherals.wishbone.WishboneSignature

Bases: Signature

__init__(wb_params: WishboneParameters)

create(*, path: tuple[str | int, ...] = (), src_loc_at: int = 0): Create a WishboneInterface.

coreblocks.peripherals package

Submodules

coreblocks.peripherals.axi_lite module

coreblocks.peripherals.bus_adapter module

coreblocks.peripherals.wishbone module

Module contents