coreblocks.priv package

Subpackages

• coreblocks.priv.csr package
  • Submodules
  • coreblocks.priv.csr.aliased module
  • coreblocks.priv.csr.csr_instances module
  • coreblocks.priv.csr.csr_register module
  • coreblocks.priv.csr.double_counter module
  • coreblocks.priv.csr.shadow module
  • Module contents
• coreblocks.priv.traps package
  • Submodules
  • coreblocks.priv.traps.exception module
  • coreblocks.priv.traps.instr_counter module
  • coreblocks.priv.traps.interrupt_controller module
  • Module contents
• coreblocks.priv.vmem package
  • Submodules
  • coreblocks.priv.vmem.translation module
  • Module contents

Submodules

coreblocks.priv.pmp module

class coreblocks.priv.pmp.PMPChecker

Bases: Elaboratable

Implementation of physical memory protection checker. This is a combinational circuit with return value read from result output.

Effective mode depends on mode: - LSU: MPRV-aware (using MPP when MPRV=1 and current mode is M) - INSTRUCTION_FETCH: uses only current privilege mode - MMU: always behaves as supervisor mode

In machine mode, accesses bypass PMP by default (result = 1/1/1) unless a matching locked entry (L=1) is found. S/U-mode accesses default to no access (0/0/0) if no entry matches.

Attributes

paddrSignal

Memory address, for which PMP checks are requested.

resultPMPLayout

RWX permission bits for the given address based on current PMP configuration and privilege mode. Bits are set to 0 if access is denied.

__init__(gen_params: GenParams, *, mode: PMPOperationMode) → None

class coreblocks.priv.pmp.PMPLayout

Bases: StructLayout

__init__()

class coreblocks.priv.pmp.PMPOperationMode

Bases: Enum

INSTRUCTION_FETCH = 2

LSU = 1

MMU = 3

Module contents