coreblocks.frontend.decoder package
Submodules
coreblocks.frontend.decoder.decode_stage module
- class coreblocks.frontend.decoder.decode_stage.DecodeStage
Bases:
ElaboratableSimple decode unit. This is a transactional interface which instantiates a submodule InstrDecoder. This InstrDecoder makes actual decoding in a combinatorial manner.
- __init__(gen_params: GenParams, get_raw: Method, push_decoded: Method) None
- Parameters
- gen_paramsGenParams
Instance of GenParams with parameters which should be used to generate fetch unit.
- get_rawMethod
Method which is invoked to get raw instruction from previous step (e.g. from fetch unit) it uses FetchLayout.
- push_decodedMethod
Method which is invoked to send decoded data to the next step. It has layout as described by DecodeLayouts.
coreblocks.frontend.decoder.instr_decoder module
- class coreblocks.frontend.decoder.instr_decoder.InstrDecoder
Bases:
ElaboratableClass performing instruction decoding into elementary components like opcodes, funct3 etc. It uses combinatorial connection via its attributes.
- Attributes
- instr: Signal(gen.isa.ilen), in
Instruction to be decoded.
- opcode: Signal(Opcode), out
Opcode of decoded instruction.
- funct3: Signal(Funct3), out
Three bits function identifier.
- funct3_v: Signal(1), out
Signals if decoded instruction has funct3 identifier.
- funct7: Signal(Funct7), out
Seven bits function identifier.
- funct7_v: Signal(1), out
Signals if decoded instruction has funct7 identifier.
- funct12: Signal(Funct12), out
Twelve bits function identifier.
- funct12_v: Signal(1), out
Signals if decoded instruction has funct12 identifier.
- rd: Signal(gen.isa.reg_cnt_log), out
Address of register to write instruction result.
- rd_v: Signal(1), out
Signal if instruction writes to register.
- rs1: Signal(gen.isa.reg_cnt_log), out
Address of register holding first input value.
- rs1_v: Signal(1), out
Signal if instruction takes first input value form register.
- rs2: Signal(gen.isa.reg_cnt_log), out
Address of register holding second input value.
- rs2_v: Signal(1), out
Signal if instruction takes second input value form register.
- imm: Signal(gen.isa.xlen), out
Immediate values provided in instruction. If no immediate values were provided then value is 0.
- succ: Signal(FenceTarget), out
Successor for FENCE instructions.
- pred: Signal(FenceTarget), out
Predecessor for FENCE instructions.
- fm: Signal(FenceFm), out
Fence mode for FENCE instructions.
- csr: Signal(gen.isa.csr_alen), out
Address of Control and Source Register for CSR instructions.
- optype: Signal(OpType), out
Operation type of instruction, used to define functional unit to perform this kind of instructions.
- illegal: Signal(1), out
Signal if decoding of instruction was successful. If instruction do not fit into any supported instruction type for selected core generation parameters t then value is 1.
coreblocks.frontend.decoder.instr_description module
- class coreblocks.frontend.decoder.instr_description.Encoding
Bases:
objectClass representing encoding of single RISC-V instruction.
- Parameters
- opcode: Opcode
Opcode of instruction.
- funct3: Optional[Funct3]
Three bits function identifier. If not exists for instruction then None.
- funct7: Optional[Funct7]
Seven bits function identifier. If not exists for instruction then None.
- funct12: Optional[Funct12]
Twelve bits function identifier. If not exists for instruction then None.
- instr_type_override: Optional[InstrType]
Specify InstrType used for decoding of register and immediate for single opcode. If set to None optype is determined from instrustion opcode, which is almost always correct.
- rd_zero: bool
rd field is specifed as constant zero in instruction encoding. Other fields are decoded accordingly to InstrType. Default is False.
- rs1_zero: bool
rs1 field is specifed as constant zero in instruction encoding. Other fields are decoded accordingly to InstrType. Default is False.
coreblocks.frontend.decoder.rvc module
- class coreblocks.frontend.decoder.rvc.InstrDecompress
Bases:
Elaboratable- instr_mux(sel: Value, inputs: list[amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable | tuple[amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable]]) tuple[amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable]