coreblocks.func_blocks.fu.lsu package

Submodules

coreblocks.func_blocks.fu.lsu.dummyLsu module

class coreblocks.func_blocks.fu.lsu.dummyLsu.LSUComponent

Bases: FunctionalComponentParams

__init__(*, result_fifo: bool = False) → None
get_decoder_manager()
get_module(gen_params: GenParams) → FuncUnit
get_optypes() → set[coreblocks.arch.optypes.OpType]
class coreblocks.func_blocks.fu.lsu.dummyLsu.LSUDummy

Bases: FuncUnit, Elaboratable

Very simple LSU, which serializes all stores and loads. It isn’t fully compliant with RiscV spec. Doesn’t support checking if address is in correct range. Addresses have to be aligned.

__init__(gen_params: GenParams, bus: BusMasterInterface) → None
Parameters
gen_paramsGenParams

Parameters to be used during processor generation.

busBusMasterInterface

An instance of the bus master for interfacing with the data bus.

coreblocks.func_blocks.fu.lsu.lsu_atomic_wrapper module

class coreblocks.func_blocks.fu.lsu.lsu_atomic_wrapper.LSUAtomicWrapper

Bases: FuncUnit, Elaboratable

Wrapper for LSU that adds support for atomic operations.

It provides simplified implementation of atomic operations under assumptions that:

  • LSU doesn’t reorder memory accesses, like in LSUDummy

  • There is only one hart

AMO operations issue two independent accesses (unless there is an exception) to LSU and execute operations in the internal ALU. SC are only matched to LR, reservation set size is infinite.

Behaviour of atomic insturctions on Memory Mapped I/O space is currently undefined.

__init__(gen_params: GenParams, lsu: FuncUnit)
class coreblocks.func_blocks.fu.lsu.lsu_atomic_wrapper.LSUAtomicWrapperComponent

Bases: FunctionalComponentParams

__init__(lsu: LSUComponent, *, result_fifo: bool = False) → None
get_decoder_manager()
get_module(gen_params: GenParams) → FuncUnit
get_optypes() → set[coreblocks.arch.optypes.OpType]
lsu: LSUComponent

coreblocks.func_blocks.fu.lsu.lsu_requester module

class coreblocks.func_blocks.fu.lsu.lsu_requester.LSURequester

Bases: Elaboratable

Bus request logic for the load/store unit. Its job is to interface between the LSU and the bus.

Attributes
issueMethod

Issues a new request to the bus.

acceptMethod

Retrieves a result from the bus.

__init__(gen_params: GenParams, bus: BusMasterInterface, depth: int = 4) → None
Parameters
gen_paramsGenParams

Parameters to be used during processor generation.

busBusMasterInterface

An instance of the bus master for interfacing with the data bus.

depthint

Number of requests which can be send to memory, before it provides first response. Describe the resiliency of LSURequester to latency of memory in case when memory is fully pipelined.

check_align(m: TModule, funct3: Value, addr: Value)
postprocess_load_data(m: ModuleLike, funct3: Value, raw_data: Value, addr: Value)
prepare_bytes_mask(m: ModuleLike, funct3: Value, addr: Value) → Signal
prepare_data_to_save(m: ModuleLike, funct3: Value, raw_data: Value, addr: Value)

coreblocks.func_blocks.fu.lsu.pma module

class coreblocks.func_blocks.fu.lsu.pma.PMAChecker

Bases: Elaboratable

Implementation of physical memory attributes checker. It may or may not be a part of LSU. This is a combinational circuit with return value read from result output.

Attributes
addrSignal

Memory address, for which PMAs are requested.

resultView

PMAs for given address.

__init__(gen_params: GenParams) → None
class coreblocks.func_blocks.fu.lsu.pma.PMALayout

Bases: StructLayout

__init__()
class coreblocks.func_blocks.fu.lsu.pma.PMARegion

Bases: object

Data class for physical memory attributes contiguous region of memory. Region of memory includes both start and end address.

Attributes
startint

Defines beginning of region, start address is included in the region.

endint

Defines end of region, end address is included in the region.

mmiobool

Value True for this field indicates that memory region is MMIO.

__init__(start: int, end: int, mmio: bool = False) → None
end: int
mmio: bool = False
start: int

Module contents