coreblocks.priv.traps package

Submodules

coreblocks.priv.traps.exception module

class coreblocks.priv.traps.exception.ExceptionInformationRegister

Bases: Elaboratable

ExceptionInformationRegister

Stores parameters of earliest (in instruction order) exception, to save resources in the ReorderBuffer. All FUs that report exceptions should report the details to ExceptionCauseRegister and set exception bit in result data. Exception order is computed in this module. Only one exception can be reported for single instruction, exception priorities should be computed locally before calling report. If exception bit is set in the ROB, Retirement stage fetches exception details from this module.

__init__(gen_params: GenParams, rob_get_indices: Method, fetch_stall_exception: Method)

coreblocks.priv.traps.exception.should_update_prioriy(m: TModule, current_cause: Value, new_cause: Value) → Value

coreblocks.priv.traps.instr_counter module

class coreblocks.priv.traps.instr_counter.CoreInstructionCounter

Bases: Elaboratable

Counts instructions currently processed in core. Used in exception handling, to wait for core flush to finish.

Attributes

incrementMethod: Increments the counter. Should be called when new instruction leaves fetch stage.
decrementMethod: Decrements the counter, and returns if the counter will be equal to zero after that cycle (it was the last instruction in core and no new instruction is fetched). Should be called when instruction is retired.

__init__(gen_params: GenParams)

coreblocks.priv.traps.interrupt_controller module

class coreblocks.priv.traps.interrupt_controller.InternalInterruptController

Bases: Component

Core Internal Interrupt Controller Compatible with RISC-V privileged specification. Operates on CSR registers xIE, xIP, and parts of xSTATUS. Interrups are reported via plain signals in Component interface.