coreblocks.priv.csr package

Submodules

coreblocks.priv.csr.aliased module

class coreblocks.priv.csr.aliased.AliasedCSR

Bases: CSRRegister

Temporary simple support for CSR aliasing for InternalInterruptController. Will be replaced with more complete implementation soon.

__init__(csr_number: Optional[int], gen_params: GenParams, width: Optional[int] = None)

Parameters

csr_number: Optional[int]: Address of this CSR Register. If None is given, CSR is virtual - not automatically connected to CSRUnit.
gen_params: GenParams: Core generation parameters.
width: Optional[int]: Width of CSR register. Defaults to xlen.
ro_bits: int: Bit mask of read-only bits in register. Writes from _fu_write (instructions) to those bits are ignored. Note that this parameter is only required if there are some read-only bits in read-write register. Writes to read-only registers specified by upper 2 bits of CSR address set to 0b11 are discarded by CSRUnit.
init: int | Enum: Reset value of CSR.
fu_write_priority: bool: Priority of CSR instruction write over write method, if both are called at the same cycle. If ro_bits are set, both operations will be performed, respecting priority on writeable bits. Deafults to True.
fu_write_filtermap: function (TModule, Value) -> (ValueLike, ValueLike): Filter + map on CSR writes from instruction. First Value in returned tuple signals if write should be performed, second is modified input data.
fu_read_map: function (TModule, Value) -> (ValueLike): Map on CSR reads from instructions. Maps value returned from CSR.
src_loc: int | SrcLoc: How many stack frames deep the source location is taken from. Alternatively, the source location to use instead of the default.

add_field(bit_position: int, csr: CSRRegister)

add_read_only_field(bit_position: int, bit_width: int, value: int | enum.Enum)

coreblocks.priv.csr.csr_instances module

class coreblocks.priv.csr.csr_instances.DoubleCounterCSR

Bases: Elaboratable

DoubleCounterCSR Groups two CSRRegisters to form counter with double isa.xlen width.

Attributes

increment: Method: Increments the counter by 1. At overflow, counter value is set to 0.

__init__(gen_params: GenParams, low_addr: CSRAddress, high_addr: Optional[CSRAddress] = None)

Parameters

gen_params: GenParams: Core generation parameters.
low_addr: CSRAddress: Address of the CSR register representing lower part of the counter (bits [isa.xlen-1 : 0]).
high_addr: CSRAddress or None, optional: Address of the CSR register representing higher part of the counter (bits [2*isa.xlen-1 : isa.xlen]). If high_addr is None or not provided, then higher CSR is not synthetised and only the width of low_addr CSR is available to the counter.

class coreblocks.priv.csr.csr_instances.GenericCSRRegisters

Bases: Elaboratable

__init__(gen_params: GenParams)

class coreblocks.priv.csr.csr_instances.MachineModeCSRRegisters

Bases: Elaboratable

__init__(gen_params: GenParams)

coreblocks.priv.csr.csr_register module

class coreblocks.priv.csr.csr_register.CSRRegister

Bases: Elaboratable

CSR Register Used to define a CSR register and specify its behaviour. CSRRegisters are automatically assigned to CSRListKey dependency key, to be accessed from CSRUnits.

Examples

# Timer register that increments on each cycle and resets if read by CSR instruction
csr = CSRRegister(1, gen_params)
with Transaction.body(m):
    csr_val = csr.read()
    with m.If(csr_val.read):
        csr.write(0)
    with m.Else():
        csr.write(csr_val.data + 1)

Attributes

read: Method: Reads register value and side effect status. Side effect fields read and written are set if register was accessed by _fu_read or _fu_write methods (by CSR instruction) in a current cycle; they can be used to trigger other actions. Always ready.
read_comb: Method: Reads register value or value submitted by _fu_write`(instruction write) combinationally. Note that returned value ignores priority setting. It allows for `_fu_write -> read_comb -> write operation in single cycle. Note that if _fu_write is called, it returns call value ignoring ro_bits. Always ready.
write: Method: Updates register value. Always ready.
_fu_read: Method: Method connected automatically by CSRUnit. Reads register value.
_fu_write: Method: Method connected automatically by CSRUnit. Updates register value. Always ready.

__init__(csr_number: Optional[int], gen_params: GenParams, *, width: Optional[int] = None, ro_bits: int = 0, init: int | amaranth.lib.enum.Enum = 0, fu_write_priority: bool = True, fu_write_filtermap: Optional[Callable[[TModule, Value], tuple[amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable, amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable]]] = None, fu_read_map: Optional[Callable[[TModule, Value], amaranth.hdl._ast.Value | int | enum.Enum | amaranth.hdl._ast.ValueCastable]] = None, src_loc: int | tuple[str, int] = 0)

Parameters

csr_number: Optional[int]: Address of this CSR Register. If None is given, CSR is virtual - not automatically connected to CSRUnit.
gen_params: GenParams: Core generation parameters.
width: Optional[int]: Width of CSR register. Defaults to xlen.
ro_bits: int: Bit mask of read-only bits in register. Writes from _fu_write (instructions) to those bits are ignored. Note that this parameter is only required if there are some read-only bits in read-write register. Writes to read-only registers specified by upper 2 bits of CSR address set to 0b11 are discarded by CSRUnit.
init: int | Enum: Reset value of CSR.
fu_write_priority: bool: Priority of CSR instruction write over write method, if both are called at the same cycle. If ro_bits are set, both operations will be performed, respecting priority on writeable bits. Deafults to True.
fu_write_filtermap: function (TModule, Value) -> (ValueLike, ValueLike): Filter + map on CSR writes from instruction. First Value in returned tuple signals if write should be performed, second is modified input data.
fu_read_map: function (TModule, Value) -> (ValueLike): Map on CSR reads from instructions. Maps value returned from CSR.
src_loc: int | SrcLoc: How many stack frames deep the source location is taken from. Alternatively, the source location to use instead of the default.

coreblocks.priv.csr package

Submodules

coreblocks.priv.csr.aliased module

coreblocks.priv.csr.csr_instances module

coreblocks.priv.csr.csr_register module

Module contents