coreblocks.priv.vmem package

Submodules

coreblocks.priv.vmem.iface module

class coreblocks.priv.vmem.iface.TLBBackingDevice

Bases: Protocol

Protocol for devices that can be used as a backing device for TLBs.

__init__(*args, **kwargs)

accept: PROVIDED: 1>]

Method for accepting a translation response. Expected layout is AddressTranslationLayouts.tlb_accept.

request: PROVIDED: 1>]

Method for requesting a translation. Expected layout is AddressTranslationLayouts.tlb_request.

coreblocks.priv.vmem.tlb module

class coreblocks.priv.vmem.tlb.FullyAssociativeTLB

Bases: TLBBackingDevice, Elaboratable

Fully associative TLB capable of same-cycle operations. Meant for L1 TLBs.

__init__(gen_params: GenParams, *, entries: int, backing_resolver: TLBBackingDevice, perf_name_prefix: str = 'mmu.tlb')

class coreblocks.priv.vmem.tlb.SetAssociativeTLB

Bases: TLBBackingDevice, Elaboratable

__init__(gen_params: GenParams, *, entries: int, ways: int, backing_resolver: TLBBackingDevice, perf_name_prefix: str = 'mmu.tlb')

coreblocks.priv.vmem.translation module

class coreblocks.priv.vmem.translation.AddressTranslator

Bases: Elaboratable

Address translator from virtual to physical addresses.

__init__(gen_params: GenParams, *, mode: AddressTranslatorMode) → None

class coreblocks.priv.vmem.translation.AddressTranslatorMode

Bases: Enum

INSTRUCTION = 1

LSU = 2

coreblocks.priv.vmem.walker module

class coreblocks.priv.vmem.walker.PageTableWalker

Bases: TLBBackingDevice, Elaboratable

Hardware page table walker for RISC-V virtual memory translation.

This module implements a page table walker that translates virtual page numbers (VPN) to physical page numbers (PPN) by walking through the page table hierarchy according to the current SATP configuration.

Supported virtual memory modes: - BARE: No translation (immediate page fault) - SV32: 32-bit virtual addresses, 2-level page table - SV39: 64-bit virtual addresses, 3-level page table - SV48: 64-bit virtual addresses, 4-level page table - SV57: 64-bit virtual addresses, 5-level page table

Implements Svade semantics (exception on missing A/D bits).

__init__(gen_params: GenParams, bus: BusMasterInterface) → None

Module contents